Adithya Adavalli
Adithya Adavalli
FPGA Design Engineer
> Strong Background in FPGA full product cycle development (synthesis, timing, placing & routing).
> 2 years of RTL coding experience using Verilog.
> 1 year of professional experience in developing High speed Digital designs on FPGA’s (Virtex-7) for a high frequency trading firm.
> 1 year of academic experience in developing Digital designs on FPGA’s (Spartan-6, Spartan-3/3E).
> Demonstrated ability to debug complex FPGA’s using chip-scope and verification tools.
> Experience using IO Serdes, UART, DSP resources, internal memory resources on FPGA’s and high speed transceivers.
> Ability to develop digital systems that need strict timing constraints.
> Excellent team player and self-starter with good ability to work independently and possess good analytical, problem solving and logical skills.

(618) 303-6537
Fremont, CA 94555

FPGA Design Engineer Anova Technologies Chicago, IL
June 2014 to November 2015
> Worked for Financial Trading Firm (R&D dept.) and responsible for FPGA full product cycle development including RTL coding (Verilog), synthesis, placing and routing, static timing analysis and testing.
> Worked under the guidance of a senior scientist on a research topic called Metastability to improve latency.
> Analyzed Metastability behavior in FPGA€™s at high frequency asynchronous clocking frequencies (up to 640MHz) and their adverse effects on High speed logic designs.
> Achieved methodology to eliminate Metastability, where I used completely different approach to save latency (without a need for additional clocks) to achieve error free efficient data transfer at high speeds between two FPGA’s.
> Established communication between two FPGA€™s using shared LVDS pairs in DNV7F2A.
> Tested signal integrity of 10GB & 1GB signal passing through trans-receiver with optical fiber cable channel.

Graduate Assistant NIU DeKalb, IL
December 2013 to May 2014
Tools used: Spartan-6, Microsoft Visual C#, UART cable, Xilinx ISE
> Worked under the guidance of Professor Dr. Reza Hashemian to create a GUI for Data Transfer between FPGA and PC (Personal Computer) and also responsible for maintaining IC Design Laboratory.
> Developed windows PC application for data transfer between FPGA and PC through UART cable using C# and Verilog code and now user can send all files including Image files to FPGA memory (CRAM) and data from FPGA memory can be transferred to PC by pushing a button.

Graduate Student NIU DeKalb, IL
September 2013 to December 2013
Tools used: Spartan-6, Spartan-3, Ps2 keyboard, Xilinx ISE simulator, Hyper Terminal/Real term
> Designed and developed a verilog code using Xilinx ISE simulator, such that FPGA device accepts all the keys typed on the keyboard.
> Functioning of the code is verified by connecting UART cable to the PC and Installing real term/Hyper terminal software on PC, so that the characters typed on the keyboard are displayed on real term/Hyper terminal window.

Undergraduate Student KITS Warangal, Andhra Pradesh
August 2012 to April 2013
Tools used: Matlab
> Created a robust and accurate Interactive Image segmentation based on convex active contour model.
> In the initial step we have to draw the foreground and background strikes on the Image using user interface tools that we have developed using Matlab. In subsequent stages only the foreground image is extracted based on algorithms which we developed.

Summer Intern Medha Servos Hyderabad, Andhra Pradesh
May 2012 to December 2012
> Assisted Engineers who developed Vigilance Control Device (VCD) a micro-controller based safety device which will automatically apply penalty brakes when driver is anticipated or dead.
> Developed a system that gives cyclic warnings to the Driver, along with that we coded Atmega-32 micro-controller based on driver’s response to cyclic warnings, In case if he fails to address those warnings automatically safety brakes are applied.

Obstacle avoiding Robot, KITS, Warangal KITS, Warangal
September 2010 to December 2010
Equipment required: Atmega32, 12v motors-2, IR-Sensors-2
> The two wheeled obstacle avoiding robot avoids obstacles that come across its way. When an obstacle is present in front of it, the light gets reflected from the object and IR receiver senses it and the microcontroller takes respective action like changing the path of robot.

Undergraduate Researcher – Electric bike KITS, Warangal Warangal, Andhra Pradesh
September 2009 to December 2009
Tools used: 180 watt motor, 12v Battery, dynamo, manual 6-speed gear system.
> Designed an electric bike by fixing a 180 watt motor and a power supply of 12v; initially battery charges through normal Power supply, later it is charged by dynamo, torque and speed can be varied by manual gear system.

Master of Science Electrical Engineering Northern Illinois University
DeKalb, IL
May 2015

Bachelor of Technology Electronics and Communication Engineering Kakatiya Institute of Technology and Science
Warangal, Andhra Pradesh
May 2013

Verilog, VHDL, OrCAD, Matlab, C, C++, C#, System Verilog, TCL, SPICE, WINAVR, BASH, 8085/8086 Assembly Language

Tools Worked on: Virtex-7, Spartan-6, Spartan-3/3E, Altera, Vivado 2014.1, Xilinx, Silvaco, Xilinx ISE 14.7, Modelsim,
Active HDL Linux, Github, Modelsim, Oscilloscopes, and Function generators.
Applications: MS Word, Excel, PowerPoint, Visio.

  • Updated 7 years ago

To contact this candidate email

Contact using webmail: Gmail / AOL / Yahoo / Outlook

This entry was posted in . Bookmark the permalink.