Carol Anderson

Carol Cacic Anderson
5844 Dufferin Dr, Savage MN 55378
Home: (952)440-5642 Cell: (612)807-4385
cacic@yahoo.com
www.linkedin.com/in/carolcacicanderson

Technical Skills
System level signal integrity analysis Tools: HSPICE(Synopsys),
PCB design and layout Allegro(Cadence), SI_Wave(Ansys),
Failure analysis through simulation of both Spectre(Cadence), Calibre(Mentor Graphics),
large and small scale circuits PADS(Mentor Graphics), Python, Verilog
Feasibility studies to verify performance Semiconductor lab and test experience
requirements for DDR and NAND interfaces providing insight when problem solving and
Responsible for PCB build and verification a foundation for innovation
Experience
Silicon Space Technology November 2014 to Current
Sr ASIC Design Engineer
Bloomington, MN
Responsible for layout and build of PCBs
Interfaced with vendors for packaging, wafer dicing, and PCB build
Verification testing of PCBs and SOCs
LSI Logic / Avago Technologies January 2009 to November 2014
ASIC R&D Engineer Sr
Mendota Heights, MN
Perform system level signal integrity analysis of DDR and NAND interfaces.
Provide layout guidance of IC package and PCB layout for optimum signal integrity performance.
January 2005 to December 2008
ASIC Customer Engineer Sr
Test vector generation.
Test insertion.
HSPICE support.
April 1999 to December 2004
Senior Design Engineer
Design, layout, and characterize I/O buffers, library, and support cells.
Make necessary modifications to 3rd party IP and analog circuits, enabling automated place and
route.
December 1993 to April 1999
Mask Designer
Layout and verify analog circuit, I/O buffers, library cells, and support cells

Honeywell Corp August 1988 to December 1993
Research Engineering Technician
Bloomington, MN
Layout and verify GaAs ICs.
RF and DC test of GaAs ICs.
Saw, package, and bond devices.
Unisys / Sperry / Univac Corp April 1983 to August 1988
Research Technician
Eagan, MN
Photolithography, etch, metalization, and diffusion CMOS and GaAs processes.
SEM failure analysis of CMOS and Bipolar processes.
Layout, verify, RF and DC test of GaAs ICs.
Accomplishments
Patent
Voltage Tolerant Oscillator Input Cell : LSI Logic : US 6181214 B1 : Issued 2001

Publications
Ka-Band High Efficiency Power Amplifier MMIC with 0.3um MESFET for High-Volume
Applications : Honeywell : IEEE Transactions on Microwave Theory & Techniques : 1992 : ISSN
0018-9480
MESFET MMIC Ka-Band Transmitter Performance for High-Volume System Applications :
Honeywell : IEEE Journal Solid-State Circuits : 1992 : ISSN 0018-9200

Awards
Alpha Team Award : Honeywell ; 1990
Winner Circle Award : LSI Logic ; 2000
Education
University of Wisconsin
Computer Science
Madison, Wisconsin
Engineering Prerequisite Coursework – 1 year
University of Minnesota
Electrical Engineering
Minneapolis, Minnesota
Electrical Engineering Coursework – 2years
Professional Affiliations
IEEE Member
References
References are available upon request.