525 Harriet Ave, Shoreview, MN∙ 55126∙ 614-477-6694∙ email@example.com
EE professional with 2 year+ experience in Analog/Mixed-signal/RF IC design, hardware/firmware design & test. Solid understanding of CMOS, Analog, RF Circuits, ADC/DAC.
EDA Tool: Cadence Virtuoso, Spectre, MATLAB, Altium Designer, LTspice, SimVision, Modelsim
Programming: C/C++, Verilog-AMS, VHDL, MSP430 Code Composer, LabView, UNIX Shell scripting
Lab Equipment: Oscilloscope, Function generator, Spectrum analyzer, Modulation domain analyzer, Logic Analyzer
IC Design Engineer, Medtronic, Mounds View, MN Dec. 2014 – Pressent
• Performed industry leading pacemaker mixed signal IC design and verification.
• Cross-functional worked with test engineers, product engineers, system engineers and technicians to develop new generation pacemaker system level and production tests.
Hardware Engineer, Medtronic, Mounds View, MN Feb. – Dec. 2014
• Performed pacemaker mixed signal IC system emulation utilizing hardware acceleration technology.
• Supported PCB designer and system engineer for system emulation platforms development.
• Validated RF telemetry system between implanted device and instrument on application layer using System C.
Product Development Engineer, TE Connectivity, Menlo Park, CA Oct. – Dec. 2013
• Performed power electronics PCB system design and validation.
• Completed technical documents, including design specification, test report, BOM, etc.
Graduate Student Researcher, OSU ElectroScience Lab, Columbus, OH Jan. – May. 2013
• Performed RFIC design, including LNA, VCO, and Mixer, from initial evaluation to schematic simulation and verification using Cadence Virtuoso & SpectreRF for 90nm process.
• Worked on CMOS device, S-parameter, noise analysis, and transmission line; balanced tradeoffs to meet specifications.
MS, ECE The Ohio State University, Columbus, OH Aug. 2013
BS, EE Shanghai University of Electric Power, Shanghai, China Jun. 2011
PROJECTS & RESEARCH
Polaris Pacemaker Mixed Signal IC Integration Oct. 2015 – Present
• Performed integration of pacemaker Incremental ADC and Heart Impedance Measurement block.
• Built transistor level test bench for ADC in Cadence Virtuoso & Spectre to determine specific issues.
• Conducted chip level simulation using pacemaker Verilog-AMS model to determine timing issues of ADC.
Orion Inc. 2 Pacemaker Verilog-AMS Verification Sep. 2015 – Present
• Integrated and verified pacemaker Verilog-AMS model, including Pacing Engine, Sense Amplifier, DSP block, etc.
• Conducted chip level verification on Ventricular Capture Management and Sense Amplifier modules with SimVision to assist production tests and system emulation with other departments.
SubQ Pacemaker Prototype Design Nov. 2014 – Sep. 2015
• Designed Shock Detector prototype board, including concept review, schematic simulation, PCB design and specification tests, to deliver human heart shock detection and capture.
• Utilized MSP430 MCU, Bluetooth module and other electronic components based on schematic simulation in LTspice.
• Implemented specification and quality tests using LabView and lab equipments, processed data with MATLAB.
• Evaluated the proposed Shock Detector transistor level model in Cadence Virtuoso.
Galaxy Mixed Signal IC Emulation Jun.– Oct. 2014
• Designed hierarchical RTL models of Sense Amplifier and Electrogram Magnetic frontend in Cadence Virtuoso.
• Integrated the model with SDC ADC model, and synthesized in Cadence Palladium HW accelerator.
• Input digitized pacemaker lead signals generated by MATLAB, and verified its functionality using SimVision.
IRIS+ Electric Vehicle Charging System PCB Design Oct.– Dec. 2013
• Performed comprehensive electric vehicle charging system PCB design using LTspice and Altium Designer.
• Conducted quality tests according to safety standards such as UL and VDE.
• Performed electronic components selection, board bring up and hands-on system debugging.
Voltage Controlled Oscillator Design Jan.– Jun. 2013
• Designed LC-VCO for GSM upper frequency bands (DCS1800 & PCS1900) with tuning range of 1.6-2GHz.
• Employed Gain-boosting level locked loop to achieve 3MHz/V supply pushing.
• Achieved significant close-in -118dBc/Hz @ 0.4MHz & & far-out -155dBc/Hz @ 20MHz phase noise.
Low Noise Amplifier Design Jan.– Jun. 2013
• Designed 3-10GHz ultra wideband LNA using resistive feedback with gm-enhanced cascade topology.
• Completed whole block including 50 Ohms input and output match network designing.
• Balanced the tradeoff while achieving 5dB noise figure, 15dBm minimum gain & -5dBm IIP3.
Mixer Design Jan.– Jun. 2013
• Designed active Mixer for direct conversion receiver covering UMTS I-IV bands (1.8-2.2GHz).
• Employed double balanced structure and achieved IF bandwidth with 5MHz.
• Balanced the tradeoff with 10dB noise figure, 12dB conversion gain, 10dBm IIP3 & 52dBm IIP2.
Operational Amplifier Design Sep.– Dec. 2011
• Designed folded-cascade differential OpAmp using Cadence Analog Artist for AMI 0.6um technology.
• Balanced tradeoff among 50dB gain, 300kHz bandwidth, 65 degrees phase margin, and 0.9mW power dissipation.
• Employed miller compensation capacitor to maintain its stability as a unity gain buffer.
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