SOFTWARE MANAGER, SYSTEM ENGINEER
Technical team leader of embedded software, robust systems (e.g.; medical; financial; sales demo), and
complex systems (distributed; high performance; instrumentation).
Range of successful custom product deliveries include a 400-core processor chip, an award-winning
chemistry robot, quarterly product refresh at a top-tier PC manufacturer, a hand-held battery-powered
database, an automatic ventilator for surgery patients who cannot breathe for themselves, and blood oxygen
measurements via stickers.
Looking for the next complex problem to tame and the next team to grow into mastering it.
C, C++, C#, Python, Matlab, R, Mathematica, make, assembly, UNIX/Linux/Windows/RTOS
applications/boot/services, UNIX/Linux/Windows shell/scripting, Verilog for ASIC and FPGA.
Presentations, training, technical pre-sales, technical writing.
NONIN MEDICAL, Plymouth, Minnesota • 2009-present
A developer and manufacturer of noninvasive blood oximetry medical products, with 250 employees.
Software and Mathematics Manager, Advanced Technology (April 2015-present)
Led a team of 6 to do proof of concept and machine learning — design of experiment, data collection and
analysis, model exploration and fitting, and some real-time software customization — to develop next-gen
measurements that are the core of new products.
Principal Staff Engineer and Software Manager, Research (March 2014-March 2015)
Worked with the founder to develop proof of concept prototypes of new measurements for demonstration
to and evaluation by potential customers: some embedded software coding and sensor design, but
mostly machine learning (design of experiment, clinical data recording, model exploration and analysis,
curve fitting, accuracy analysis, separation of variance).
Principal Software and System Engineer, Product Development (November 2009-March 2014)
Subject matter expert for real-time embedded software and optical measurements using LEDs and
photodiodes to estimate blood oxygen levels from outside the skin. Introduced design by contract and
defensive programming to the software engineers. Introduced the ability to emulate algorithm results
from previous clinical data recordings. Finished the conversion of the primary trade secret algorithm from
assembly to C (for microprocessor portability) and designed the verification method to pass the
regulatory requirement of substantial equivalence. Noticed data integrity problems in the clinical
recording software, then initiated and completed a project to fix the problem. Helped develop the next-
gen platform of measurement hardware and software to span all previous measurements and most of
the foreseeable ones with a single platform. Designed the hardware/software interface of new digital
logic for faster data transfer yet deeper sleeping to save microprocessor power.
DIRK HELGEMO • Page 1 • DirkHelgemo@yahoo.com
LOGIC PRODUCT DEVELOPMENT, Minneapolis, Minnesota • 2006-2009
A consultant developer and low-volume manufacturer of custom industrial and medical products, with
Principal Software and System Engineer
Developed electronic gadgets for customers: Collected/analyzed/prioritized market and technical product
requirements. Researched and chose hardware and software technologies based on features and
budget. Managed multidisciplinary projects (primary disciplines were electrical, software, and mechanical
engineering). Developed pre-sales budget/schedule/feature proposals, and tracked and reported
progress during implementation. Implemented software/firmware, delivered prototypes, debugged
hardware and software problems, and delivered working units. Member of the software process
improvement committee to achieve ISO 9001 and ISO 13485.
• Technical lead to design and implement a chemistry mixture separation machine (liquid flash
chromatography) that was awarded R&D 100 in July 2009: Architected the electromechanical
subsystems (stepper motors for pumps and arms, fluid valves, laser sensor, and UV spectrometer), the
user experience (both the GUI and physical interactions with the system), and the software architecture
(GUI, robot state machine, and drivers in .NET and real-time motor control in FPGA).
• Upgraded hardware and ported software of a medical ventilator (will breathe for patients when they stop
breathing for themselves): redesigned the electronic safety features (ECC on RAM, watchdog) and
software mitigations (handle correctable ECC errors, reset on watchdog failure) to be appropriate for the
failure modes of the new hardware.
• Developed an interactive/robotic sales demo system using a PC (for audio, video, and touch-screen
GUI) and a custom USB microprocessor board (for real-time control of the device being sold).
• Applied RFID to a manufacturing process, from raw material lot tracking to final goods inventory.
COREDGE NETWORKS, Minneapolis, Minnesota • 2006
A telecommunications start-up company with 20 employees: Develops control systems and routing
processors for AdvancedTCA and MicroTCA high availability chassis.
Senior Staff Engineer, Software and System
Evaluated implementing 10 gigabit per second network processing (switching, routing, and/or endpoint
acceleration) in an FPGA (a programmable hardware chip). Designed efficient hardware/software
interfaces to manage nineteen platform management buses with a single soft CPU in an FPGA.
Analyzed standards (AdvancedTCA, MicroTCA, XAUI/Ethernet, PCI Express, RapidIO, IPMI, IPMB, and
I2C) to determine product requirements, specifications, and test plans.
MATHSTAR, Minneapolis, Minnesota • 2002-2005
A fabless semiconductor start-up company with 80 employees: Developed a custom 400-core 1 GHz
processor chip (a denser, faster version of an FPGA) that surpassed competing performance by 5x.
Chief Architect and Software Manager
Led the hardware architecture team to design the communication infrastructure and processor cores.
Led the software team to develop the tools suite to program and simulate the chip hardware (SystemC
IDE and assembly). Presented the technology to investors, conferences, and customers. Wrote the
patent application for the hardware communication infrastructure. Developed sample applications to
demonstrate product advantages.
Key Accomplishments: (See next page.)
DIRK HELGEMO • Page 2 • DirkHelgemo@yahoo.com
MATHSTAR Key Accomplishments:
• Developed the hardware communication infrastructure: a regular array of 400 square processor
elements that communicates primarily with nearest neighbors, but sometimes far away (such as I/O).
• Evaluated the differences between having all-purpose processor cores vs. a few special-purpose types.
Selected four special-purpose types, and implemented three of them.
• Noticed group superstitions for choosing processor core features, then developed models to quantify the
effects of changing them (bus width, number of registers, number of instruction types, number of
instructions per processor, etc.). Most parameters moved away from their “superstition” values.
• Defined the programming concept and syntax for each processor type and I/O block.
• Separated place & route syntax from processor behavior (so that cycle behavior and resource allocation
decisions can be made somewhat separately).
• Established decision metrics for chip size and processor mix, evaluated and refined a number of
possibilities, and helped the executive team decide to fabricate two chips (same size, different mixes).
• Developed internal tools used to verify chip operation during design, and to validate the chip in the lab.
• Wrote essays, was accepted, and then presented to 5 national conferences: Microprocessor Forum,
HPEC at MIT, IEEE-SoC, DARPA (DoD), and MAPLD (NASA).
• Developed a 3-day training course, and presented to 5 customer companies and 3 internal groups.
• Delivered cycle-accurate programming and simulation tools to customers (multiple releases).
• Key technical and marketing contributor to IPO materials.
• The chip worked. After adding a metal layer for power and using flip-chip packaging, it worked at speed.
TERAGO COMMUNICATIONS, Minneapolis, Minnesota • 2000-2002
A fabless semiconductor start-up company with 100 employees: Developed the industry’s first network
processor chip able to classify and route and meter 10 gigabits per second.
Led the firmware team of 16 developers to develop APIs to program the network processor chip, the 8-
port fabric interface chip, and a content-addressable memory. Actively participated on all chip
architecture teams, a designated expert for the hardware/software interface boundary. Helped design,
validate, and productize line cards and systems (prototype router components). Developed chip and
system demonstrations. Presented to investors, press, and customers.
• Designed and implemented the software library that customers used to program the network processor
chip, the 8-port fabric interface chip, and a 2-port content-addressable memory (for network processor
lookups). Integrated a third-party software library for a framer chip.
• Developed thorough validation tests for all chips and boards (using the software libraries).
• Developed a firmware code and build environment for C and C++ that is adapted to different operating
systems and CPUs. (Ported to Linux, Solaris, eCos, and VxWorks Oses. Ported to x86, Sparc, and
ARM CPUs.) This mechanism enabled software libraries and applications to be developed with chip and
board simulations. Once chips and boards were available, the libraries, tests, and demos were
recompiled, fixed, and running in less than a day.
• Planned and produced seven firmware releases.
• Helped architect the router demo hardware: dual mesh of 16 network processors on hot-swappable
cards with redundant fabric, power, cooling, and monitoring/control systems.
• Designed and developed hot-swappable peer-to-peer messaging for the discovery, monitoring, and
control of all properties of all boards in a system. Used shared memory, PCI, and UDP for transport.
• Led the development of realistic demonstrations of the network processor chip handling real-world
routing challenges at speed from/to a 10 gigabit per second network traffic tester.
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GATEWAY, North Sioux City, South Dakota • 1999-2000
A top-tier build-to-order PC manufacturer of 5,000 employees and $8 billion annual revenue.
Senior Project Engineer, Graphics
Subject matter expert for consumer graphics processors: Worked with marketing, sales, manufacturing,
and supplier management to choose graphics card vendors and features for quarterly refresh across
three subsegments of the consumer market: entry-level, mainstream, and enthusiast (gamer).
Surpassed competitors in graphics features; yet satisfied the cost, volume, and flexibility requirements of
a large manufacturing operation. Discussed and influenced next-generation graphics features with
vendors: digital display 1400×1024 and higher (which became DVI), HDTV input and output, velocity
awareness (for motion blur and automatic dynamic detail), curved surface geometry, and stereo vision.
Researched emerging graphics technologies (geometry acceleration, motion blur, efficient spatial
antialiasing). Technical contributor for Gateway video products: TV tuner, DVD hardware and software,
1394 and USB, and digital cameras.
EARLIER ROLES: (Details available upon request.)
• Principal Software Engineer, Security for Datacard (credit card security, Minneapolis, 1998-1999)
• Senior Software & ASIC Engineer for Artist Graphics (3D graphics, Minneapolis, 1996-1998)
• Senior Software Engineer for Digi International (NT driver for serial port cards, Minneapolis, 1995-1996)
• Senior Software Engineer for Blue Ridge Software (NT encrypting firewall, Monticello, IL, 1993-1995)
• Software Engineer for Addamax (UNIX kernel security for DoD, Champaign, IL, 1991-1993)
• Intern for Northwestern Mutual Life Insurance (actuary, Milwaukee, WI, 1990)
RIPON COLLEGE, Ripon, Wisconsin • 1991
Bachelor of Computer Science and Mathematics
• Completed a four-year degree with two majors in six semesters with a GPA of 3.94 (of 4.00).
• Graduated with honors, Summa Cum Laude, and Phi Beta Kappa.
• Mathematical Contest for Modeling (international undergraduate contest by ORSA, SIAM, and COMAP):
awarded Outstanding in 1991 (one of the six published entries), and Honorable Mention in 1990.
• National Science Foundation — Honorable Mention in Computer Science.
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