Jerome Claxton

Resume of:
Jerome D. Claxton
3810 France Ave. South
Saint Louis Park, MN 55416-4912
HOME: 952.920.5271

Electronics PCB Design: 38 years’ experience. Medical / RF / Analog / High Speed Digital
Integrated Circuit Designer: 3 years’ experience.
System Administrator : 26 years experience.
Founder & President of the Minnesota Chapter of the IPC Designers Council. 1996 -1999
EE Cad systems used:
Cadence: Allegro, Concept, Composer, Virtuoso, Design Planner; Mentor Graphics: Board Station, IC Station, Calibre Tanner: Ledit, View Logic: Powerview, Workview; Pads: Pads, DxDesiger Blaze, Pspice, HSpice; SciCards, Pcad, Tango, IBM CDBS 2, CV 4X, Redac, Calma GDS 2, ILE, Design Capture, CAE, Orcad, Daisy Logician, Calais, & Telesis.
Mechanical Cad systems used: Pro-E, Applicon Bravo, CV 4X, Autocad, Drafix
Operating Systems used: Windows10-Windows XP, 2000, NT, SUN Solaris, SUN OS, HP-UX, Ultrix, VAX, PDP, DOS.

3/17/2003 – Present CommScope Inc. / TE Connectivity / ADC Telecommunications Inc.
ADC Telecommunications Inc. was sold to TE Connectivity in 2010
TE Connectivity was sold to CommScope in 2015

Title: Senior Printed Circuit Designer CID+
Duties: Lead Designer of high density, RF, Analog, and High Speed Digital 10Gb, Controlled Impedance, double sided surface mount boards. Signal integrity calculations, simulation & verification. Designs were in Cadence Allegro, Concept HDL, Orcad CIS, and Pads with 1,500 pin count FPGAs, BGAs, Differential Pairs, Matched Clock Lengths, Rocket I/O, 75% Class constrained per IPC & UL specifications. Schematics were 5-29 pages using Concept, Orcad CIS, DxDesigner. Performed ECAD Management functions including Librarian, Software Administrator, developed process & quality improvement plans, ProE Interface, Agile & SAP implementation. Mechanical layout & design using ProE, Sheetmetal, Pro Cable, Assemblies, Model Automation. Added responsibilities component engineering, & environmental engineering (RoHS, WEE & Reach) SAP & AGILE Interface development. Received IPC CID + accreditation.
8/5/0002 – 12/31/2002 Techpower Inc. (Contract)
ADC Telecommunications Inc.
Title: Printed Circuit Designer C.I.D.
Duties: Layout of high density single sided HDSL2 and HDSL4 boards Using Mentor Graphics Board Station. Boards consisted of 4 layer Digital & Analog Surface Mount circuitry per IPC & UL specifications.

7/30/01 – 5/31/02 Terago Communications
Title – Senior IC Mask Design Engineer
Duties: Full custom IC Layout of 40Gbps Network Processor consisting of 6 layer, Mixed Signal, 2 GHz Serial/Deserializer, PLL, & 8×10 Bit Shift circuits using Tanner Ledit & Mentor Graphics IC Station for layout, and Calibre DRC & LVS for verification. All layout was netlist driven from View Logic using Hspice. I also edited Calibre rule decks for TSMC 0.18MM Mixed Signal Process. Terago went out of business

2/26/99 – 7/21/01 Xiotech Corporation
Title – Senior Printed Circuit Designer; C.I.D.
Duties: Design of High Speed Analog / Digital double sided surface mount boards using BGAs with pin counts up to 456 pins with 0.5mm pitch. High speed Fibre Channel Arbitrated Loop boards at frequencies up to 2.125 GHz, 96 Differential Pair signals routed to 1 mil length tolerances. Processor boards using Intel’s i80960 architecture.2.125 GHz Back panel designs utilizing 32 Disk Drives. I was the UNIX Software Administrator, Cadence Software Administrator and Librarian. I also used Concept and migrated all UNIX designs to Windows NT.

5/27/97 – 2/24/99 Angeion Corporation
Title – Senior Printed Circuit Designer / Integrated Circuit Designer
Duties: Design of dense Analog / Digital ICs, & ceramic, flex, and FR-4, hybrid circuit boards for implantable medical devices. IC designs were Analog / Digital with pin counts up to 156. Board designs were Analog / Digital, RF, and High Current applications composed of 2 – 10 layers with b/b vias, double sided surface mount, die mount / wire bond, BGAs, & FPGAs. I was the Cadence Software Administrator, & Librarian. Mechanical drawings were created as 3D solid models in Pro-E.

2/10/97 – 5/24/97 Advance/Possis (contract)
Teradyne Corp.
Title: Senior Printed Circuit Designer
Duties: Design of 2.1 GHz Clock board using high speed digital, ECL, Differential Pairs on double sided surface mount boards for integrated circuit testing. Designs were up to 16 layers with BGAs, PGAs, with component counts of 3000+, using Concept for schematic capture and packaging, & Allegro for board design with a Specctra router.

11/06/95 – 2/3/97: Itron inc.
Title: Senior Printed Circuit Designer
Duties: Design of RF & A/D double sided surface mount ceramic boards for remote data acquisition products using View Logic for schematic capture and SciCards for PCB layout. I set up a component library and an engineering data structure. Maintained Sparc 1000, for ~30 users in two sub-domains using NIS+, and administered, Solaris, View Logic, SciCards, ProE, Hspice,. I assisted in PC administration

01/07/89 – 11/03/95: Westinghouse/Thermo King Division
Title: Senior Designer, Electrical / Mechanical
Duties: Design of digital/analog multilayer surface mount & double sided PCBs, electrical diagrams, wire harness drawings and mechanical packaging in compliance with IPC standards for microprocessor controls, data acquisition & satellite communications, in high current, vibration & EMI environments using Allegro, Concept, Composer and View Logic. I also maintained the software licenses and performed software updates on HP 9000s, DEC stations, and PCs. Mechanical designs were sheet metal and plastic, using PRO-E & Bravo 3,

10/20/87 – 11/23/88: Possis Engineering (contract)
Unisys Corporation
Honeywell USD
Title: Printed Circuit Designer
Duties: Design of high density double sided surface mount ceramic with conductive ink boards using 12 to 48 layers in compliance with MIL-STDs.

04/04/86 – 10/17/87: Senior Design Corporation (contract)
Micro Component Technology, TSI
Title: Printed Circuit Designer
Duties: Design of TTL/ECL & CMOS multilayer PCBs for velocimetry equipment and integrated circuit test equipment.

12/28/82 – 03/26/86: Zycad Corporation
Title: Design Automation Specialist
Duties: Design and simulation of high speed logic simulation systems.

08/01/82 – 12/20/82: Senior Design Corporation (contract)
Medtronic
Title: Mechanical Designer
Duties: Tool design for Energy Technology Division

10/02/79 – 07/29/82: Control Data Corporation, Advance Design Lab,
Title: Printed Circuit Layout
Duties: Layout, digitizing, tape-ups, schematics & logic drawings for the Cyber 205 and Star 100 systems.

01/04/79 – 10/17/79: Univac
Title: Printed Circuit Layout
Duties: Tape-ups, schematics & wire wrap sequencing for mainframes & back panels in support engineering.

07/01/78 – 12/31/78: Possis Engineering (contract)
Micro Component Technology
Title: Layout Electrical Draftsman
Duties: Schematics, logic diagrams & wiring diagrams

Educational background:
Richfield High school, Graduated 1973
Minneapolis Area Vocational Technical Institute (Electronics, Associate Degree) 1975-1977
Occupational Skills Training Center (Drafting) 1978
St. Paul Technical Vocational Institute (CAD Systems ) Computer Vision and Tri-Ac systems)1981
RF & Analog Design Methodologies (Copper Connection) 1996
High Speed Circuit Design Methodologies (IPC) 1998
IPC Designer Accreditation CID (IPC) 2000
IPC Designer Accreditation CID + (IPC) 2004

Thank you,
Jerome Claxton
3810 France Avenue South
Saint Louis Park, MN 55416-4912
HOME: 952.920.5271
JerryClaxton55416@msn.com