1020 Elm St Apt. 4, San Jose, CA 95126 +1 (408) 221-3273
Website – www.shrirajkunjir.technology email@example.com
High-energy professional with an infectious enthusiasm for technology seeking challenging opportunities.
Master of Science in Electrical Engineering, Santa Clara University, Santa Clara, CA GPA: 3.55 June 2015
Key Courses: VLSI Design, Logic Design Using HDL, Modern Timing Analysis, Logic Analysis and Synthesis, Review
of UVM and OVM, Computer Architecture, DSP Design in FPGA, Design for Testability, VLSI Physical Design, Low
Power Design of VLSI Circuits, SoC Formal Verification Techniques, Semi-Custom Design with Programmable
Devices, High Level Synthesis, Secure Coding in C/C++, Operating Systems, RF Microwave and Systems
Bachelor of Engineering in Electronics and Telecommunication, University of Pune, India GPA: 3.6 June 2013
Specialities ASIC RTL Design, CMOS Design, Digital Logic design, SoC Design & Integration, Test Bench
Development, Assertions, Synthesis, Static Timing Analysis, Place & Route, Functional & Formal
Verification, Lint, Validation, Physical Design, Layout Design, Computer Architecture
Languages Verilog, SystemVerilog, Matlab, Assembly, C, VHDL, C++
FPGA Tools Altera Quartus II, Xilinx Vivado, Lattice Diamond
Synopsys Tools VCS, Design Compiler, Formality, PrimeTime
Other Tools Matlab Simulink, Mentor Graphics ICStudio, GNU Debugger, QtSpim, Multisim, MS Visio
Environment Linux, Macintosh, Microsoft Windows
Infinera (ASIC Design Intern), Sunnyvale, CA June 2014 – Sept 2014
ü Proof of concept of SONET/SDN pointer justification algorithms used in next generation 100G and 200G ASICs
ü Extensively worked on clock domain crossing, timing closure and post-silicon validation.
ü Implemented the algorithms in a mapper/de-mapper block of two different ASICs and mapped it on an FPGA and
POC board (board bring-up). Responsibilities included – block-level RTL design, functional design verification by
writing different test cases in SystemVerilog, preparing the design for synthesis, performing static timing analysis
and FPGA pin mapping in Altera Quartus II and validating the design in lab under different test conditions to meet
specific target PPM constraint. Gained knowledge of different frame formats and protocols like Ethernet and OTN.
ü Worked in a cross-functional team of system architect, design, verification and overseas engineers in different
phases of the project and contributed significantly towards the development of the chip.
Design and verification of asynchronous Encoder and Decoder with random error injection in Verilog
ü Designed the scheme using (8,4) hamming function capable of error detection and correction. Implemented
synchronizers on the receiver side. Developed testbench in Verilog and performed static timing analysis.
Design and verification of Single Cycle Control and Datapath of 32bit MIPS Processor in Verilog
ü Designed, implemented and simulated different components including control unit, data memory, instruction
memory, ALU and adder to emulate operations like instruction fetching, opcode decoding and data read/write.
Formal Verification of IP core of AMBA – AXI bus protocol in Verilog
ü Performed formal verification using Formality between RTL and netlist and by introducing an error in the RTL and
having the tool catch the error. Synthesized netlist using Leonardo spectrum and Design Compiler.
FPGA realization of an 8×8 switch router in Verilog
ü Verified the design for different configurations and synthesized netlist to realize the FPGA implementation in Lattice
Diamond. Determined the fastest speed of operation by tightening the timing constraints.
Design and verification of asynchronous FIFO in Verilog/SystemVerilog
ü Designed a synthesizable FIFO in Verilog with different flags like full, empty, almost full/empty, half full. Developed
testbench in SystemVerilog, used assertions and performed timing closure.
Full Chip Physical Design of Dual port RAM in Verilog
ü Designed a dual port RAM in Verilog, synthesized the netlist in Leonardo Spectrum and performed placement &
routing, floorplanning, port placement, LVS and DRC checks on the layout design in MentorGraphics tool chain.
Schematic and Layout design of 4-bit Manchester Carry Chain Full Adder
ü Used Mentor Graphics – IC Studio tool to design schematic and layout of a 4-bit Manchester Carry Chain Full Adder
using tsmc 35um design technology and performed transient analysis, DRC and LVS checks.
Secure coding in C and C++
ü Wrote code to check vulnerabilities based on stack and heap based buffer overflow, format string exploits, pointer
manipulation, code injection and use of mitigation strategies for these exploits.