Siva Sai Teja Akunuru
469-286-5957 | email@example.com
800 W Renner RD, Richardson, TX www.linkedin.com/pub/siva-sai-teja-akunuru
1+ years’ experience in FPGA and Hardware oriented Development, Seeking Full-Time/Intern opportunities for spring 2016 in Digital
Design, Embedded and FPGA prototyping, Hardware Integration and verification
Capgemini India Pvt Ltd, Bangalore – Embedded Software Engineer June 2013 – June 2014
– Oversaw functional development of FPGA and Digital integrated Circuits. Independent handling, debugging and software/firmware
design and development of medium sized embedded applications.
CS Outreach, University of Texas at Dallas – Instructor July 2015-Present
– Tutor Embedded programming with Arduino and Raspberry pi and interactive level programming tools like Alice, 123Autodesk along
LI2-Innovations Pvt Ltd – Technical Intern Aug 2012
– Worked with USART, I2C, SPI, USB, PCIe, DDR,CDN and Interface of RTC IC on an Atmel Atmega32 Microcontroller. Created In-system
programming in AVR Studio 4 for peripheral subsystems with lab equipment like Oscilloscopes, Function generators
Hindustan Aeronautics Ltd – Research trainee June 2011 – Aug 2011
Technologies Xilinx ISE, ModelSim, HSPICE, Synopsys PrimeTime, Design Vision, Cadence Encounter, MATLAB, TetraMAX
Languages C, C++, Verilog, RTL, VHDL, SystemVerilog, Assembly level programming, Shell Scripts, Python, PERL, Make file
Operating Systems Windows, Unix
Certification: SOC Verification using SystemVerilog, Python Programming by Coursera
Master of Science, Electrical Engineering in Digital Systems May 2016
The University of Texas at Dallas, Richardson, TX 3.3 GPA
Coursework Computer Architecture, VLSI Design, Advanced Digital Logic, ASIC Design(Audit), Design and Analysis
of Reconfigurable Systems, Design Automation, Microprocessors, Digital Signal Processing, RF and Microwave Systems,
Linear systems, Testing and Testable Design, Active Semiconductors.
– Design of Data memory Accessor using CADENCE and EDA Tools
• Implemented standard cell library in Cadence Virtuoso. Checked for LVS and DRC, Characterized cells, generated .lib files
• Synthesized RTL design in Xilinx ISE, Floorplanning, placed and route, clocking and timing closure, Power, Static Timing analysis in
IBM 130nm CMOS technology.
Results: Number of Cells: 2412, Power: 9.34µW Area: 143842 µm2
– Designed 16-bit Pipelined Microprocessor
• Designed Harvard Architecture to perform assembly instructions with Branch control flags on Xilinx ISE and Hardware emulation on
Nexys™4 DDR Artix-7 FPGA using Keyboard and Monitor in Verilog
– Simulated Annealing for circuit Bi-partition
• Determined best Cutset using extracted data from the raw Benchmark Netlist and Area files.
• Implemented Placement engine utilizing Simulated annealing for standard cell placement and Floor planning using C/C++
– ATPG using TetraMAX with Fault and Pattern Repot Generation
• Determined ATPG for several Combinational Circuits using TetraMAX by Synopsys
– Reverse engineered 32-bit ARM processor on Nexys™3 Spartan-6 FPGA Board,
• Detection and Execution of Fibonacci series using Verilog code on FPGA board.
– Implemented Euclidean Algorithm to find GCD and RTL design for Babbage Difference Engine which tabulates polynomial functions on
Nexys™4 DDR Artix-7 FPGA Board
– Low power Mini Stereo Digital signal Audio processor (ASIC Design)
• Designed MSDAP with specifications of lowpower and Low-cost with a functionality of FIR filter of 2 channels and 255 order.
• Behavioral modeling of MSDAP was simulated and verified in Verilog on Xilinx ISE, implementing a RTL model of the same and
producing a synthesized design and then developed a layout using Encounter
– Cache Design using Simple scalar
• Determined CPI and fine-tuned the cache hierarchy of Alpha microprocessors of 3 individual bechmarks: GCC Anagram and GO