” To be part of an organization that encourages self innovation and that rewards creativity and hard work.”
San Jose, CA 95112
Design Engineer SSR Labs, Inc. San Jose, CA
July 2015 to Present
Working on Design of an SRAM cache plus cache controller of vlcRAM module using Verilog HDL.
Responsible to write test bench and different test plan for verification of Hybrid Memory Cube(HMC) module
Verilog HDL, System Verilog, Synopsys Design Vision, Xilinx ISE
Instructional Student Assistant San Jose State University San Jose, CA
February 2014 to May 2015
Responsible to teach ModelSim and Xilinx ISE to students.
Occasionally take lectures and help professor in grading.
MS Electrical Engineering San Jose State University
San Jose, CA
2013 to 2015
B.E. Electronics & Communication Engineering G.H.Patel College of Engineering & Technology, S.P. University.
2007 to 2011
RTL Design, State Machine Diagram, Pipelining, ASIC/FPGA Design, Synthesis, Signal Integrity, Verification, Timing Analysis, Digital Logic Design, APB, AHB, PCI-x, PCIe, Python, Verilog, VHDL, Event Management, Supervising
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