Thomas Ferreras

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Thomas Ferreras
Last updated: 09/04/15

Job Title: no specified
Company: no specified
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Forked River, NJ 08731

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Resume Headline: Ferreras Thomas 8.01.15 Resume Value: 2wy9t6f9aiygpnyy

THOMAS FERRERAS?H 609-693-3749 ?C 609-312-8445 ?

?H 609-693-3749 ?C 609-312-8445 ? ? 311 Wainwright Street ? Forked River, NJ 08731

Top-performing professional with extensive experience in product design to production and support. Expertise in system architecture encompassing mixed-signal hardware and firmware. Design background in embedded processors, microprocessors and programmable gate arrays (PGA) with communications, security, vision and military applications. With integrated peripheral analog, digital and mixed-signal. Steering them to products from conception to production on time and within budget.
Excellent problem-solving and troubleshooting skills, impeccable attention to detail, and exceptional project administration capabilities. Demonstrated abilities in devising/implementing corrective and preventive actions to ensure conformance to all standards and regulations. Valued contributor to engineering teams with commitment to continuous improvement and customer satisfaction.
Skill set includes:
? Research & Development (R&D)
? CAD Layout & Routing
? Testing Methodology
? Product Launch
? Part Prequrement
? Root Cause Analysis
? Quality Control/Assurance
? Leadership & Teambuilding

Protocols: VoIP, TCIP, UDP, SONET, CDMA, Project 25 (Public Safety), TD-LTE, M2M, IoT High Speed Interface: Ethernet 10/100/1G/10G, USB 2.0, USB 3.0, PCI, PCIe, WI-FI, Bluetooth, BLE, Zigbee, Video Interface: BT.656, BT.1120, 8/16-bit CMOS, HDSDI, HDMI, NTSC Serial Interface: UART, USB Serial (UART), I2C, SD, SPI, CT bus (H.110), IPMB (IPMI) Processor (8–64 bit) MCU, DSP, and ARM: TI, Freescale, Intel, Atmel, Altera, Samsung, ST, Marvell, Cypress, Xilinx Programmable Logic Family: Altera, Xilinx, Actel Languages: VHDL, Verilog, C, C++, Assembly Operating Systems: Windows, Linux, Android, U-Boot CAD Tools: PADS, OrCAD, ALTIUM, CADSoft EAGLE, CAM 750 Design Tools: PSpice, MathCAD, MathWorks, ModelSim, Quartus II, ISP Foundation, Eclips Tools and Software: Adobe Creative Suite, PDF Writer, Microsoft Office Suite, Visio and Project
Passport Systems ? Billerica, MA April 2015 to Present
Senior Design Engineer: Contracted by Black Diamond to Passport Systems Inc. Bring up from prototype not power up to completed with new FPGA platform with a NIOS II processor, command and control firmware (VHDL)/software (C) and solve all hardware problems. Solve and log all issues and update schematics.
• RICDOR-Slave platform: The RICDoR-Slave has 32 analog sensor filters and 128 computer with D/A set points. Controlled by a ALTERA Cyclone III FPGA with a NIOSII controller running, serial RS484 interface to a system controller Linux PC and a future expansion port to RICDoR-Master.
• IP controller: All VHDL, C blocks are designed to meet a standard IP format for Passport Systems.

JuST Engineering ( Forked River, NJ May 2014 to Present
Senior Design Engineer: Contractor with Engineering group that handles everything from concept to production.
• EMC FCC Class A compliance PCB 8 layer redesign. Review design and test data then restructure FPGA (ALTERA Cyclone V) PLL, DDR3, Analog Sensors, LiPo charging/management system add adjusting termination and layers. New board passes FCC class A. June 2014 to July 2014
• HD Video to Camera Link. This is 1080p HDSDI Video input to Camera Link with an ALTERA Cyclone IV controlling all video sizing and compression. Design, routed and manufactured 6 boards. Setup a custom UBOOT and Linux embedded development system. July 2014 to September 2014
• M2M architecture and specification. Wi-Fi, Bluetooth Package and personal tracker for hospital and patient temperature and heartbeat. Extremely light weight and rechargeable. July 2014 to October 2014
• ELTA North America. Architecture, specification and design work on federal business opportunities request for information on RF, analog and cables contracts December 2014 to February 2015
• 5M Video over WIFI with Robotic pay load. This is single board video and Robotic MPU (CC3200 (ARM Cortex M4)) with a WIFI internal core. The PCB is lightweight with low price BOM Spare Time, May 2014 to February 2015
• Fire Safety Iot System. Architected and prototype a WIFI/BLE slow scan 2Mpix video recognition system. The primary function was reading an analog meter with a very low data rate and extreme low power. May 2015 to Present
Magnolia Broadband? Englewood, NJ 2013 to May 2014
Senior Digital Design Engineer: Primary function of the team is to produce communication patents and Proof of Concept (PoC) to increase performance (IP) and advanced features. The Primary IP is a small cell eight channel TD-LTE, 8×8 channel digital beam forming. Lead baseband architecture the PoC is made up or two high speed mixed signal boards named BS board and Radio board.
• BS Board is a simulated Base Station in side an ALTERA Cyclone V FPGA. The FPGA is memory mapped to nine DAC all channels matched impedance and trace length, nine high speed serial ADC and all Radio board Transceivers. With the Radio board controlled by SPI master. All data flow is controlled by the CPU module connected to USB serial, USB 2.0, USB OTG & Ethernet 10/100 ports. PCB is 16 layer board routed for 10 GHz.
• Radio Board is nine independent duel band transceivers with one used to calibrate the others. All controlled by the BS board FPGA with an ALTERA MAX V CPLD. PCB is an 8 layer with 9 isolated radios routed for 10 GHz.
DesignLinx Hardware Solutions ? Nashua, NH 2012–2013
Design Engineer: Contract engineering company hardware and firmware design. Primary function is to design from specification to production. I was certified professional by Altera and Xilinx.
• . Designed for SRI an Acadia II 25g digital development board with 3 light weight cameras with different wave lengthy imagers. Using a cadence orcad schematic capture system and mentor pads layout tools.
• Redesigned for BAE an FPGA to modify function on an existing board.
• Designed for BAE an FPGA IP camera core from specification document.
• Designed from specification firmware for a cypress psoc1 3 phase motor controller. With a 10 gram production PCD in production

SRI International – Sarnoff Products & Services Division ? Princeton, NJ 2009–2012
Senior Electronic Engineer: Responsible for Acadia Product line development platforms, production, customer support and member of R&D development team.
• Acadia Single-Chip Video Processor: Advanced vision fabric with PPC8270 controller including PCI and ADP versions with 2 analog input channels NTSC/PAL. Redesigned fixing obsolescent components to fit in same housing.
• Acadia II System-on-a-Chip (SOC): Low power and low latency advanced vision technology device controlled by ARM11 quad core that performs real-time video enhancement, stabilization, multi-sensor fusion, stereo range estimation, and image feature detection with three 16-bit video inputs, OVL, and three 8-bit link video outputs.
• Acadia II System-on-a-Module (SOM): SOC with 4 DDR2-SDRAM chips, FLASH memory, and 2 USB 2.0 PHY interface with low power configuration that can be plugged into career boards to support different video inputs and outputs including Acadia II Development Platform, Compact Vision System Digital/Analog, and Compact Vision System Camera Interface. Developed the schematics and setup layout and controlled routing. Designed to solve all the high speed problems developed schematics and layout controlled routing.
• Acadia II SOM Analog Development Board.
• Acadia II SOM Digital Development Board
• Acadia ILS: Architected and developed series commercial product using Acadia II stabilizer IP on a DSP including:
– ILS-6000, Roget NTSC/PAL stabilizer one channel analog in to analog out with bypass on power or command.
– ILS-6100, OEM NTSC/PAL stabilizer printed circuit board designed for integration into camera enclosures, pan-tilt units, robots, and unmanned vehicles.
– ILS-6200, multichannel universal rack mount configuration that fits to standard 19” rack with 4–8 ILS-6100 (one per channel)
– ILS-6500, CMOS/BP.656 to H.264 compressed video over IP stabilizer.
LG Electronics USA – IRIS Division ? Cranbury Township, NJ 2008–2009 Senior Design Engineer, R&D Division: Lead R&D design engineer on advancing biometric iris recognition capture and matching engine with emphasis on security and zero percent false match failure rate.
• Upgraded and repaired ICAM4000 (IRIS biometric camera unit) to enhance reliability and decrease price of components; replaced obsolete compounds, streamlined design from 4 boards to 2, resolved temperature and hermetic issues, and corrected versos document, library, and compound problems.
• Designed new 7000 series line of products, writing architecture and memory maps for proposed systems and completing pricing study for marketing personnel and upper management.
• Worked independently on I-See system concept and Altera Cyclone IV FPGA and 5M pix imager project using NOIS II microcontroller to capture and store image frames 30 fps and transfer 5 frames with highest contrast. Developed proof of concept schematics, layout and routing.

TruePosition ? Berwyn, PA 2007–2008
Senior Digital Designer, R&D Division: This division primary responsible to design next generation on cell phone tracking and location system named E911. The system uses a traditional GPS and an antenna triangulation and beam worming. With the new system made up of two boards digital and RF.
• Digital board. I designed and wrote the firmware to boot Freescale MPC8260 PPC and setup TI TMS320C62x DSP with a two Altera Cyclone III FPFA. Developed the embedded section of the schematics and layout controlled all section on routing.
• RF board. Wrote the firmware to load and setup all RF components. The digital board MPC8260 controls the Xilinx Spartan 3AN FPGA. Developed digital section schematic, layout and controlled routing.

IPC (formerly Orbacom) ? Jersey City, NJ 2003–2007
Senior Member of Technical Staff, Command Systems Division: This Company designs and supports 911 systems for police and Fire. The primary system is named T5 is an analog 911 PBX. Gen2 T5 brings this system in the future with an Analog to Digital convergence and Supports P25 Security for the police and fire departments.
• Gen2 T5 P25 1024 channel VOIP packet switch from T5 backplane TDM bus to Ethernet compressed and encoded. This boar has a Freescale MPC8270 PPC with DDR2, FLASH, 2 PTMC and MMI Ethernet with a U-Boot boot and Linux operating code. PCB is a 16 layer high speed board using Cadence OrCAD.
• Gen 2 T5 P24 PTMC DSP module. Architected DSP p25 compression array.
• Replaced failing PEEL CPLD from Anachip (PA7540P) on all gen 1 T5 designs. Design replacement PCB Peel with a Xilinx CoolRunner-II CPLD.
• All Gen1T5 station cards to optimize stability and eliminate obsolete parts.
Artesyn Technologies (formerly Real Time Digital) ? Wall, NJ 2002–2003
Senior Hardware Design Engineer, Communication Products Division: Designed and developed CompactPCI card with Linux-based operating system (first on Katana CompactPCI carrier card). Developed schematic and layout then routed in corporate with the following features:
• VOIP bridge for 1024 voice channels with 4 to 6 VOIP compresions.
• CompactPCI embedded processor – IBM PC440GP with 2 banks of DDR and FLASH memory
• Board that supports gigabit Ethernet switched backplane and PCI
• PICMG 2.9 system management bus, dual PTMC sites (PICMG 2.15), and computer telephony bus
• FPGA convert GMII to RMII and address switch for tree banks of FLASH memory with 20-32 bit PCI registers
• Second function to control power up and system monitor utilizing Altera NIOS core
Lucent Technologies, Inc. (formerly AT&T Bell Laboratories) ? Murray Hill, NJ 1995–2002
Member of Technical Staff: Primary function on the divisions is to develop new concepts to proof of concept. Then complete a full function and feature design into production.
• Optical Networking (ONG): Served as Architect and Design Engineer for subdivision optical cross connect (OXC) utilizing MEMS device in first completely optical dense wavelength division multiplexing (DWDM) switch. Design and develop schematics and controlee Layout and routing to incorporate the following features.
– Defined guidelines for placement and routing for 10G and 2.5G OEO packs.
– Designed and simulated ALTER FPGA to replace existing backplane TDM ASIC.
– Created high-voltage DAC board to control angles of MEMS mirrors.
– Formulated and executed test plan to verify cross connect stability at OC192 and OC48.
– Met all design goals, enabling use of single design over entire family of products (LR256, LR1024, and LR64).
• Business Solutions (now AVAYA): Functioned as Lead Designer on advanced VoIP telephone adapter research project focused on enhancing voice quality.
– Developed single-chip design to improve upon first generation’s 2-chip design using ARM 940TDMI core with DSP-1627 with internal audio interface.
– Achieved product realization of IP chip set in 4400 and 4600 series with the following phone features: USB interface, IrDA ver. 1.1 interface, and advanced speaker cavity to produce better acoustics.
– Presided over CAD layout and routing to ensure passage of EMI testing and adherence to SISPA A standard on first pass; cleared SISPA B standard on second art master.
• Consumer Products, Global Wireless Product Group: Worked as Design Engineer on TDMA and CDMA PCS and cellular band phones, filling roles as Lead Design Engineer for CDMA PCS (cellular) platform. Controlled all schematics and controlled layout and routing.

Additional experience as Design Engineer – Customer Service and Hardware Design Engineer for Ascom Timeplex and Senior
Electrical Test Engineer, Design Engineer, and Electrical Test Engineer for Marconi Circuit Technology Corporation
Bachelor of Science in Electrical Engineering, Rutgers University, New Brunswick, NJ
Electronics Technology Degree, DeVry Technical Institute, New Brunswick, NJ
Completed Graduate Courses at State University of New York at Stony Brook, Stony Brook, NY
6,163,828 – Methods and apparatus for providing multi-processor access to shared memory (1998)

Additional Info BACK TO TOP

Current Career Level: Experienced (Non-Manager)

Date of Availability: Immediately

Work Status: US – I am authorized to work in this country for any employer.

Active Security Clearance: None

US Military Service:

Citizenship: US citizen

Target Company: Company Size:

Occupation: Engineering • Electrical/Electronics Engineering

Target Locations: Selected Locations: US-NJ-Central

Relocate: No

Languages: Languages Proficiency Level
English Fluent

  • Updated 7 years ago

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