TIENG NGUYEN

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Tieng Nguyen
Last updated: 12/01/15

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Runnemede, NJ 08078
US

nguyen583@gmail.com
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Resume Headline: Tieng_Nguyen_Resume.pdf Resume Value: uzi6yi7wuvuwh6n5

TIENG D. NGUYEN1158 Bendmill Way, San Jose, CA. 95122 • Cell: (856) 796-0261 • Nguyen583@gmail.comPRINCIPAL HARDWARE ENGINEERProject Leadership / Task Management / FPGA / Ultra High Speed Board Design / Design ConsultingCAREER SUMMARYA highly accomplished Engineering Professional with a proven ability to manage all phases of hardware design, development,implementation and cost reduction. An energetic self-starter with extensive technical, project leadership and supervisoryexperience. Highly adept with leading edge electronic/logic designs (10+Gbps), re-configurable hardware algorithms in FPGA,testing, and integration towards applications in network computing and data center server to ensure projects are finished ontime and at an optimal cost. Areas of experience include:• FPGA experience included Xilinx Virtex, Altera Cyclone, and Lattice using Verilog and VHDL languages, ModelSim, NCSimand System Verilog Assertion tools for simulation, debug using ChipScope, oscilloscope and logic analyzers. Somehighlights of FPGA designs are a specialized frame relay processor, Fibre Channel link processor, SONET VirtualConcatination, interconnect system bus controller, performance and statistic controller, DSPs, and glue logics.• PCB experience included incorporation of large multiple pin count FPGAs, CPU (Motorola/Intel/PowerPC/ARM) complex,memories (RLDRAM/DDR2/DDR3) and discrete logics on high speed board designs using Allegro schematics capture,Hyperlinx for signal integrity and Ansys HFSS for ultra high speed trace (10 to 25Gbps) geometry simulation.• Signal integrity experience included trace geometry constructions. For ultra high speed signals, traces are constructed indifferential co-planar microwave structures with embedded coupling capacitors on differential signals. Verified thestructures with a S-parameter measurements of two port microwave trace structures. Determined a system channel lossbudget in dB.• PCB fabrication experience included lowest cost bare boards by fitting perfecly multiple PCBs into a panel, layersymmetry and copper balance; excellent signal integrity by defining trace geometry and PCB stack up for a controlimpedance; low coupling noises by runing traces, North-South and East-West, lowest separation rules and maintaining acontinous ground return current plane; high quality PCBs by embedding a test coupon that was not only to verify thecontrol impedance but also ensure multiple EMS suppliers to meet the same criteria; design producibility by providingrule sets for trace geometry, minimum separation, grouping, and length matching; design compliance by using Valor tocheck rule sets and IPC standards violation.• Power distribution experience included a system power design, connector and power plane impedance evaluation andPoint-of-load (POL) DC converter designs with a stability analysis on gain/phase margins.• Analog design experience included op-amp circuits, application of ADC/DAC, VCO and analog filtering designs with astability analysis on gain/phase margins using Bode diagram tools.• EMI/EMC experience included design compliance, test and fix a radiation emission, conducted emission, and ESDcontact and over-air testing.• Firmware design experience included an embedded microcontroller firmware for Cypress PSOC using Cypress PSoCDesigner tools. Also collaborated with a software team to work out issues at the interface.• Developed test methodology and test verification plan metrics for designs.• Completed many design turns using Fujitsu’s ridgid Hardware Design Life Cycle and FPGA Design Life Cycle processes.The process was not only ensured high quality designs but also emphasized on DFT, DFM, DFA and design reliability.PROFESSIONAL EXPERIENCEFujitsu Network Communi, Pearl River, NYPrincipal Hardware Engineer10/2002 – PresentSummary of work at FNC included architecture and design of various embedded processor (PowerPC/ARM/PSoC) boards,power distribution, power sequencing and reset strategies, signal integrity, PCB layer stackup and layout. Some designs had amix mode as in ROADM design. For a board design framework, a rigid Fujitsu hardware life cycle process that started from aconcept to a production was followed for design documents, DFM (components and connectors packages, board profile andcopper pattern), and DFT (configurable JTAG chain), test plan metrics and verification, prototype debug and bring-up, andassistance of test setup and support for manufacturing. For a FPGA design, a Fujitsu FPGA/ASIC design process wasfollowed with a good RTL coding style, must have a default in a CASE statement, a mix of traditional Verilog andSystemVerilog(UVM) verification. Synopsis tools were for synthesis; errors and warning reports were scanned with Perlscripts; and PAR tools were Quartus, ISE and exploring Vivado. Experiences at FNC were below.* Have designed/analyzed a new EPON design project that has 8x10G clients interfaces and 2x40G netwok interfacesusing Broadcom ARAD and Pioneer chips. Employed ANSYS HFSS to design 10Ghz pre layout traces with specificrouting patterns, trace width, trace high and trace surface roughness, trace length matching, and mix dielectric constantsof multilayer stackup.* Designed a 24-layer PCB 8-Degree ROADM board using Allego 16.5 schematics capture and constraint tools. Designed,debugged and brought up the 8-Degree optical switch board with 88 channels at 40Ghz each in a single fiber. The opticalswitch board consisted of a WSS (Finisar/JDSU), an OCM (Axsun/Photop), 1×4 optical switch and supporting electronicsfor optical power monitor. An ARM processor in 1152-pin Altera SoC Cyclone 5 performed a system performance anddiagnostics. The Cyclone 5’s ARM processor interfaced to an external DDR3 which stored a runtime controlled programafter loaded from a compressed bootrap reset routine in its flash memory. The design was supported a configurable JTAGchain, DFM, and DFT at board and system level test documents.* Took parts in creating a new FW CDS product and then designed, debugged and brought up a storage and fansubsystem. The fan system was a high voltage (-48V) analog and digital I/Os designed on a 16-layer PCB using Allegro16.5 schematics capture tool. The fan subsystem was employed a Cypress PSoC, a micro-controller, to regular fan speedbased on a sensed temperature. Wrote a C-code controlled firmware on the Cypress PSoC Designer tool to compile anddownload to internal PSoC flash memory. The firmware was a self booting, reporting interrupt events and diagnosing itshealth. The design was supported a configurable JTAG chain, DFM, and DFT at board and system level test documents.Also Coded RTL for system communication bus in Verilog, synthesized in Synopsis, and mixed traditional verilog andSystemVerilog verifications. Wrote a test plan metrics, scoreboard, for use against the verification process. Responsible todebug and bring up the FPGAs in the lab.* Performed Xilinx Virtex 6 FPGA designs for FW9500 PIUs as such OUPSR (optical unidirectional path signal redundancy)and MUX sponder. The FPGAs performed a network management and control datapath facility. RTL was coded inVerilog, synthesized in Synopsis, and mixed traditional verilog and SystemVerilog verifications. Wrote a test plan metrics,scoreboard, for use cases against the verification process. Responsible to debug and bring up the FPGAs in the lab.* Worked on cost reductions on various existing designs in FW9500 and FW4100ES ESLANSU for a high return oninvestment (ROI) with high denser FPGAs and lower layer PCB stack up for reduce cost. The design was supported aconfigurable JTAG chain, DFM, and DFT at board and system level test documents.* Brought in a Fibre Channel transport expertise to Fujitsu Network Comm (FNC) product portfolio. Led the effort to defineand architected board level and FPGA level design to transport a Fibre Channel (FC) protocol over various distances, 1Kand 8K mile links. Helped system engineers to define feature sets of FC requirements and trained design engineers onFC aspects. Then led, designed, debugged and brought up the FW4100 1G/2Gbps SANSU (storage area network serviceunit) design with five other subordinate engineers. The SANSU design was implemented on a 32-layer PCB withimpedance control for 50 ohm transmission line and 100 ohm differential lines. Also, designed -48V power bus for point ofload (POL) DC/DC converters which stepped down to 5V, 3.3V, 1.5V, 1.2V, 1.1V and 0.75V to power the SANSU board.The design was supported a configurable JTAG chain, DFM, and DFT at board and system level test documents. Codeda critical verilog blocks on a clock adaptation FIFOs and flow control and verified them in traditional Verilog test bench andModelsim.* Provided a backend support of a full hardware life cycle process of the design included writing a board description spec(HUDS), board level engineering test spec (HDVS), manufacturing board level test spec (N-spec) and manufacturingsystem level test spec (MSTS). Wrote menu driven C-functions to test the board during a hardware debug cycle anddocumented them in the N-Spec for a manufacturing test technician to test production boards.* Maintained and tracked provisions in a design through a propreitary revision control (PIMS), problem reports in Oracleproblem tracking report (PTR) and engineer change notice (ECN).* Following tools were used in 10Gbps designs, Synplify, Modeltech, Xilinx, Altera, Lattice, Verilint, Synopsis, Allegro,Hspice, ADS signal integrity tools. For a very high speed signal from 5Gpgs to 25Gbps, an ANSYS HFSS was simulated atrace geometry, layer stack up, mixed dielectric constants, and routing pattern to ensure channel losses within a channelloss budget.David Sarnoff Research Center, Princeton, NJ9/1995 – 10/2002Staff Hardware EngineerSummary of work at David Sarnoff Research Center included architecture and design of Intel 486 processor video switchboard and CPU board with proprietary DSP ASIC processors in a SIMD arrangement, power distribution utilized thick copperlayers and LDO converters, reset strategies, signal integrity, power distribution, PCB layer stackup and layout. Simulate DSPprocessor IOs and performed a static timing analysis of the processor chip. Experiences included in below.* Designed and maintained a complete end-to-end RF/HFC coax cable network for a Video-on-Demand (VOD)environment.* Investigated a low yield of cutting edge high pin count ball grid array FPGAs on PCB and documented the improveddesign process into a standard procedure for a next project.* Designed a 24-layer PCB and architected a proprietary multi-gigabit (1.25GHz and 2.125GHz Fiber Channel/ GigabitEthernet physical layer) video switch for the second generation VOD server using 500K gate Altera 10K200E with 672 pinBGA as a target device. Design included virtual output queue (VOQ) DPRAM to output data to VSC870 transceiver,external FIFO interface for retrieving packets from the VSC870, a CAM route table lookup, a ping messaging controllerbroadcasts its health status and monitors other boards’ health, and CRC generation/checking. Several embedded dualclockbuffers were used for transferring packets between the multiple clock domains, 125MHz, 66MHz, and 31.125MHz.Verification included a multi-board environment used for transferring test packets through the Vitesse VSC880 switchmodel in VHDL.* Simulated, Measured, and Created High Speed PCB with 24-layer and 50 ohm control impedance, High Frequency SignalRouting, Power Distribution, Single and Differential Termination, length matching, and crosstalk budgeting rules for allsignal frequencies, up to 2.125GHz, for the second generation of the video-on-demand server. Was a mentor to juniorengineers on the signal integrity subject.* Designed memory modules for a SIMD (parallel) processor board with 128 processors for a video simulation, a realtimevideo editing and video on demand applications.* Designed system clocks (using PLL technology) with a 2ns clock jitter throughout the system, distributed in phase 84MHz,42MHZ, and 21MHZ to synchronize a massively array processors and IO modules. Used HSPICE to simulate a clock treedistribution transmission line on backplane and plugged-in-boards for LSI Logic sea of gate ASIC chip.* Extracted and analyzed the worst case static timing and specified Processor and IO ASIC chips’ interface timing.* Verified functionalities of the array element Processor and IO ASICs using LSI sea of gates CMD design tools.* Ran HSPICE circuit simulator to verify sea of gate IO buffer capable to drive a loaded transmission line on PCB for LSILogic sea of gate ASIC chip and recommended a characterized IO buffer for use in the design.Eastern Research, Inc., Moorestown, NJ2/1994 – 9/1995Design Consultant* Designed voice call connection request processing for SS7 signaling system was based on Bell Core GR303. The callprocessing agent ran on 8 T1/E1 lines with an embedded MC68360 processor. The design was used Xilinx XC4010 toprocess 2048 On/Off Hook signals on 8 T1/E1 lines. The processed On/Off Hook signals were put on FIFO for a higherlevel processing. Xilinx XACT tools were used for the FPGA development.* Designed a high reliable derived Stratum 3 clock. The design had to meet stratum 3 requirements included BellCore 378and 1244. The design was based on redundant clock modules constantly locked in phase with an incoming stratum 3clock. When the incoming stratum 3 clock ceased, an online clock module maintained its derived clock for up to 24 hoursand less than 3ppm drift. If the online clock module failed, an offline clock module took over. The high reliable PLL designconsisted of phase counter, phase error, phase/frequency detector, clock fail detector, clock switchover, and controlcircuits all in XC4010. Xilinx XACT tools were used for the FPGA development.Gandalf Data Ltd/Infotron System Corp., Cherry Hill, NJ8/1986 – 1/1994Principal EngineerSummary of work at Gandalf/Infotron System included architecture and design of Motorola MC68020 processor frame relayboard with a custom frame relay co-processor implemented in XC4005E, power distribution utilized thick copper layers andLDO converters, reset strategies, signal integrity and PCB layer stackup. Wrote a Pascal algorithm to simulate a systembehavior of a patented QUIC bus in term of system packet memory requirements.* Designed a 12-layer PCB and architected an embedded Motorola MC68020 frame relay interface module that employed acompany proprietary cell relay switching technology. The core of the project was designed, debugged, and wrote code forthe custom frame relay preprocessor (RISC) using Xilinx XC4005E and XC3090 at 25MHZ with an external sequentialmicrocode. The custom RISC processor examined, processed frame headers, stored and forwarded frames to/from thephysical link interface. The module performed 2048 PVC connections and processed 12,000 frames/s. The simulationenvironment was based on Mentor Graphic QuickSim version 8.1.* Analyzed IO buffer memory requirement for the patented 1.2Gbps switching QUIC bus interface by writing a networksimulator in Pascal for exploring system variables such as packet sizes, number of packets, and packet transit delaythroughout the system.* Group leader in charge of two enhanced embedded products to higher performance at a lower cost on 10-layer PCBs.One was an dual link statistical multiplexer from 19.2Kbps to 64Kbps. Second project was changing the currentmultiplexer to be compatible with AT&T subrate data multiplexer. The last project was converting an existing design into ahigh performance system bus platform. Managed one-hardware and two-software engineers. Both projects were capableto carry mixed voice and data channel to PBX systems.AT&T Information System., Middletown, NJ8/1985 – 8/1986Technical Staff* Designed a 12-layer PCB and debugged a VME processor module with a 10 MHZ Motorola 68010 and a zero-wait-statediscrete memory management unit (MMU) to run the system 5 UNIX operating system. The processor module was themain element in the AT&T Network Protocol Processor (NPP) product.Burroughs Corp., Paoli, PA9/1981 – 8/1985Engineer* Designed logic gates, spice simulation, and layout of a chemical sensor processing CMOS chip. The project wasdesigned with a dynamic CMOS circuit for the VLSI design graduate course work at University of Pennsylvania.* Received an award in generating a computer algorithm in Algo language to create and verify a PROM based statemachine for in house use. The design saved company many months of MI state machine redesign.COMPUTER SKILLS:Hardware:O/S:Languages:EDA Design Tools:Analysis Tools:Office Tools:Vendors:PC, SUN Sparc, SGIUNIX, Linux, and WindowsParallel C, C/C++, Pascal, LISP, Fortran, VHDL, Verilog, System Verilog, IBIS, X86 Assembly.Cadence, Mentor Graphic, ViewLogic, VeriBest, Examplar, Synplicity, Aldec, ModelSim, XilinxFoundation, Altera Qartus II, LSI CMDE, AT&T ASIC tools, Ansoft 3-D, AMPspice2.5D, HyperLynx 2Dsignal integrity, Ansys SI and HFSS.MS Excel, Project, Visio, Chronology Timing Desinger, MatlabMS Office (Word, PowerPoint, Access, Project), FrameMaker, Acrobat writerInnoveda Viewlogic, Mentor Graphics Board Station, Synplicity, Synopsis, Avanti! (H-Spice), AMP,CadenceTECHNOLOGY EXPERIENCE:LAB Tools:In-circuit Emulators, In-circuit debugger/monitor, cPCI Bus analyzer, HP Logic analyzers,oscilloscopes, Bit Error Rate Testers, Gigabit Ethernet traffic generator/checker SmartBit, Functiongenerators, Burn-in oven, RF power measurement equipment, lasers, optical sources / powermeters, and optical attenuators.SIGNAL INTEGRITY: HP 8510 Spectrum analyzer, Tektronic 11801C TDR, Agilent VNA Communication signal analyzer,LeCroy LC584AL digital scope with jitter measurement, Avanti Hspice, AMP spice, and HyperLynx,Cadence ADS and ANSYS HFSS, Bode 100, and LeCroy SPARQ-4000e.Devices:Standards:EDUCATION:BSEEMSCSXilinx Virtex and Altera Cyclone 5 FPGA, Gate Array and standard cell ASICs, SDRAM, LVDS, ECL,PECL, CMOS, GTL, HSTL, SSTL, and TTL discrete logic SRAM, CAM, Dual-Port, FIFO, Flash,EPROM, AMD, Lattice, Cypress PLDs, MC68XXX, X86, PowerPC860, Cypress PSoC, VitesseVSC870, VSC880, Silicon Labs PLL and timing devices, Broadcom ARAD and Pioneer, and DDR3.cPCI, I2C, RS232, RS485, X.25, HDLC, TCP/IP, PCIe, SATA, SAS, Fibre Channel (SAN), MPEG-1,MPEG-2, RAID, T1/T3, ATM, SONET, OTN, CPRI (Cellular network interface).Drexel University, 1981University of Pennsylvania, 1984Control Theory and ComputingCommunication and Computational Architecture

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Current Career Level: Experienced (Non-Manager)

Date of Availability: Within 2 weeks

Active Security Clearance: None

US Military Service:

Citizenship: US citizen

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Willingness to travel: Up to 25% travel