William Wilson

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william wilson
Last updated: 04/02/13

Job Title: no specified
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Macungie, PA 18062
US

alwbw@yahoo.com
Contact Preference: Email

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RESUME

Resume Headline: william wilson Resume Value: vw44nybj52w5ry46

WILLIAM B. WILSON
4964 Briarwood Dr.
Macungie, PA 18062
(Email contact only!)

Objective:
An analog or mixed-signal circuit design position on a high-caliber
team providing complete solutions to customer problems.
An individual-contributor position focusing on system, block and/or
transistor level design is preferred.

Experience Summary:

Proven architect, ability to balance between analog and digital
partitions, and tradeoffs between CDR and equalization.
Team leader, design experience at system, block, transistor levels.
Best in-class record of fully functional first silicon over 20+ years
Published papers and patents spanning many areas of IC design.
Experienced in design and layout issues for deep submicron CMOS design.

Experience Details:

April 2012 – Present – Cisco Inc. Allentown
Team Leader, Analog CMOS circuit design

Nov 2010 – April 2012 – Lightwire, Inc Allentown, PA.
Senior Analog/MS Design Engineer

Architecture and transistor level design of BBCDRs for 10 Gb/s and
28 Gb/s NRZ data rates. Circuits done include LC tank oscillator,
D/A converters, A/D (nA to uA range) converters, sense-amp latches,
20 GHz DLL using mixers. Oversaw layout teams, helped less
experienced engineers, wrote Skill code to improve productivity,
and completed design review and design specifications documentation.

May 2005 – Oct 2010 : LSI/Agere Systems; Allentown PA.
Principle Engineer – LSI; DMTS – Agere Systems

Storage PHY Design Group.
Architected, and designed the CDR for the Shanghai family of PHYs.
Novel bang-bang phase detector and digital loop filter clock
and data recovery architecture, for data rates ranging from
1.06Gb/s FC up to 8.5 Gb/s FC. Developed novel digital phase
detector and analog circuit structures to allow the CDR to be
self-trimming with no additional test circuitry for improved jitter
tolerance performance. CDRs are described by a major customer as
the best they have seen, and as world class by all major customers.

Designed main latch core and array for each product. Designed each
major analog block in the CDR over the course of several years,
improving state of the art and design methodology along the way.
Extensive use of Ocean scripts to make simulation self testing to
allow regressions. Involved in debugging many major issues accross
the product line, including transmitter, CMU, and Rx issues.
Developed core adaptive equalization algorithms. Circuits designed
or improved include core latch, matched multi-phase GHz clock
generation and distribution, analog reference voltages. re-designed
LC tank core oscillator for one product. The CDR was fully
functional in all mask-orders, allowing for system level prove in,
and device evaluation.

Team leader. Experienced in taking a product from blank paper concept
through volume ramp. Experienced in leading technical teams up 20
people, covering analog and digital design, layout, validation,
verification, and documentation. Experienced in working with
management to provide reasonable schedule estimates, and assigning
work loads based on talent and needs of the business. Experienced in
business risk assesment. No desire to manage people.

Worked on the central, roaming, and spread spectrum interpolators.
Introduced gray coding to remove clock glitches and improve performance.
Worked through many layout and floorplan issues.

May 2002 – September 2004 : Agere Systems, Allentown, PA.
Distinguished Member of Technical Staff; Analog Design Groups

High-Speed SERDES design. Responsibilities included CDR architecture
definition and simulation, transistor-level design, silicon debug,
layout oversight, and working with other design and support
organizations to resolve customer-related issues in a time-sensitive
business.

Designed the core Clock and Data Recovery PLL for a 1-4.25 GB/s NRZ.
This included development of a phase-based simulink model for
simulating closed-loop performance of the non-linear bang-bang PLL in
reasonable simulation times. Determined all CDR small-signal and block
level requirements. Completed transistor level circuit design of
oscillator and matched phase buffers, charge pump, pfd,
OTA (dual loop pll), and filter components. Initial silicon was
fully-functional. Lead debug and re-design effort to identify root-cause
and fix parametric shortcomings.

Designed a frequency synthesizer in TSMC’s 90nm technology.
Circuits designed included oscillator, pfd, charge pump, OTA, and
filter components.

Summer 2001-May 2002: Acting Technical Manager
Agere Systems, Allentown, PA.

Responsible for a circuit design and test program development team
working on multiple projects, including voice band codecs, and
AFE’s for digital telephone and IP phone products.
Left the job by choice after realizing the job is not for me.

January 1988 -August 2001: Agere Systems, Lucent Technologies,
AT&T Bell Laboratories
Member of Technical Staff; Distinguished Member of Technical Staff

Designed a 256MHz to 1.2 GHz low-noise frequency synthesizer
Designed low noise 30dB preamp.
Designed a 70.656 MHz 50 ppm 3rd overtone crystal oscillator.
Designed multiple PLLs of 622 MHz (16 matched phases).
Designed a T1/E1 frequency synthesizer.
Lead Design Engineer 100BaseT4 Ethernet Transceiver.
Designed first fully-integrated Ethernet 10BaseT transceiver.

Mentored Liang Dai (IEEE SSCS Predoctoral Fellow in 2001).

Skills:
Working knowledge of: Skill, Matlab, Unix, Cadence

Education:
Master of Science, Electrical Engineering, May 1985.
Duke University, Durham, North Carolina
Microelectronics Center of North Carolina Fellowship
Thesis: “Charge Feedthrough in n-channel MOSFETs”

Bachelor of Science, Electrical Engineering, cum laude, May 1983.
Syracuse University, The City University
Syracuse, NY London, England

Tau Beta Pi, Eta Kappa Nu,
Top Electrical Engineering Sophomore

Publications:

“A 20 Gb/s NRZ/PAM-4 1V Transmitter in 40nm CMOS Driving a
Si-Photonic Modulator in 0.13um CMOS” ISSCC 2013

“A CMOS self-calibrating frequency synthesizer”
IEEE Journal of Solid State Circuits, October 2000.

“Measurement and Modeling of Charge Feedthrough in n-channel
MOS Switches” IEEE Journal of Solid State Circuits, December 1985.

Patents:
#4818929- Fully Differential Comparator
#5199049- Digital Carrier Detection
#5717720- Digital Data RX, Differentiating Protocols
#5942949- Self-calibrating Phaselock Loop…
#6037621- On-chip Capacitor Structure
#6040742- Phaselock Loop…
#6043715- Phaselock Loop with Static Phase…
#6114920- Self-calibrating Voltage-controlled Osc…
#6594330- Phase-locked loop …
#6668334- Apparatus for detecting clock failure…
#6876054- Integrable DC/AC voltage transformer/isolator…
#7049866- Compensating for leakage currents in loop filter…
#7106107- Reliability comparator with hysteresis
#7268631- Phase Lock-Loop with scaled damping capacitor
#7679405- Latch-based Sense Amplifier
#7680217- Methods and Systems for coding a bang-bang phase detector
#7710170- Internal Supply voltage controlled PLL…
#7787515- Method and apparatus for generation of Asynchronous clock…
#7839965- High-speed Serial Data Link…
#7844021- Method and Apparatus for clock skew calibration…
#8143696- Integrated Circuit Inductors…

Experience BACK TO TOP
Job Title Company Experience
Technical Team Leader Cisco Systems – Present

Additional Info BACK TO TOP

Current Career Level: Experienced (Non-Manager)

Years of relevant work experience: More than 15 Years

Date of Availability: From 1 to 3 months

Work Status: US – I am authorized to work in this country for any employer.

Active Security Clearance: None

US Military Service: Yes

Citizenship: US citizen

Target Job: Target Job Title: Principal Engineer

Desired Job Type: Employee

Desired Status: Full-Time

Target Company: Company Size:

Target Locations: Selected Locations: US-PA-Allentown

Relocate: No

Willingness to travel: Up to 25% travel