Winston Tan

RESUME

PERSONAL PARTICULARS
1. Name: Winston B Tan
2. Home Address: 93 Broad Street, Apt.6, Matawan, NJ 07747, U.S.A.
3. Email: win_tan@verizon.net
4. Telephone: 732-566-8986 (Home), 732-939-7288 (Cell)
5. Citizenship: U.S. Permanent Resident (Green Card Holder)

QUALIFICATIONS
1. Ph.D in Electrical Engineering, Imperial College, University of London, England
2. M.Sc in Communication Engineering, Imperial College, University of London, England
3. B.Sc (Honours) in Electronic and Electrical Engineering, University of Bath, England

SKILLS/EXPERIENCE SUMMARY
– DSP embedded software/firmware development, system design/troubleshooting, algorithm investigation/simulation using C, Assembler, Matlab, Simulink. Real-time implementations and low-level coding integrated with multi-threaded RTOS including embedded Linux platforms. Porting/integration of third-party software. FPGA design with Altera and Xilinx devices. Fixed-point DSP implementations. Verification and research using Matlab/Simulink models. TCP-UDP/RTP communications, VOIP systems, IPTV video streaming.
– DSP processing – digital filter design, noise suppression, audio coding, acoustic echo cancellation, voice activity detection, video coding, FIR/IIR filtering FFT, fast correlation, filterbanks, multirate filtering, sampling rate conversion, dynamic range compression, adaptive filtering, motion compensation, DCT, entropy coding, modulation/demodulation, PLLs, channel coding, ultrasound beam-forming
– experience with audio codecs, mobile phone, wireless speakers, downhole drilling tools, digital hearing aid, video codecs, RF network analyze, Set Top Box (STB), HDTV receivers/decoders, VOIP and video streaming (IPTV) systems, PBX.
– consultant/contractor with Texas Instruments (2012), Dolby Laboratories (2013), Baker Hughes (2014) developing/optimizing embedded software/firmware.

WORK HISTORY

1. August 2015 – November 2015
Freelance Consultancy.
Analyze and document DSP embedded code written in Assembler and C. Functionalities included noise cancellation, echo cancellation, beamforming, DFT/FFT, adaptive filtering.

2. December 2014 – March 2015
Consultant with APS Technology, Wallingford, Connecticut, U.S.A.
Develop C software and Windows DLL for real-time design of digital filters for processing of received signals from mud pulser in downhole drilling tool. Investigate various IIR and FIR filter design algorithms and implementation structures for low-delay bandpass and notch filtering of narrowband signals using Matlab and Simulink. The objective was noise reduction to improve on data symbol recovery. Intel C IPP signal processing primitives were utilized for speed optimization of the run-time filter design, with Visual Studio IDE and Windows 7 operating system.

3. March 2014-November 2014
Consultant with Baker Hughes Corporation, Houston, Texas, U.S.A.
Investigate embedded system based on ARM Cortex A-9 dual-core processor in Altera Cyclone V SoCFPGA for downhole applications. Embedded OS is Linux 3.9 SMP with software development using ARM DS-5 Eclipse. Familiarized with Yocto Project build and debugging for Linux application and kernel driver development.
Design and develop firmware for high temperature testing and power analysis of Altera’s Cyclone V FPGA device. Development was done using VHDL, Modelsim and QSYS with Quartus II IDE. The design included use of the Nios II soft processor with development using Altera SBT IDE and programming in C.
Contribute to system architectural design and firmware issues in new ultrasound imaging tool for oil and gas mining/drilling application. Investigated use of high-speed multi-channel sigma-delta ADCs, front-end filtering and pre-processing needs. Investigated high-speed serial communication links e.g. Serdes, Gbps Ethernet, LVDS. System employed multiple ultrasound transducer elements with beamforming/signal processing at 8-20 MHz.

4. November 2013 – February 2014
Consultant with Radiant Communications Corporation, South Plainfield, New Jersey, U.S.A.
Wrote application and low-level Linux kernel driver code in C for generation of pulse-width modulated signals for infra-red remote control in high-definition video encoder product. Implementation was on ARM Cortex-A9 core in TI Da Vinci DM365 multimedia SoC, using interrupts and DMA data transfers. Integrated application code into existing media server on embedded Linux system of target device.

5. July 2013 – October 2013
Consultant with Dolby Laboratories, San Francisco, California, U.S.A.
Modified/added C code to implement new low-latency mode of Dolby Digital Plus audio compression encoder.
Performed optimizations in encoder code and algorithm for bit allocation to improve on speed in Dolby Digital (AC-3) encoder. Evaluated sound quality based on ITU-R PEAQ standard.
Programming environment was Microsoft Visual Studio with Intel C compiler and Perforce source control.

6. May 2013 – July 2013
Consultant with Radiant Communications, Massapequa, New York, U.S.A.
Troubleshoot and resolve issues in embedded C programs for implementation and control of broadcast HDTV encoder (featuring H.264/MPEG-2/AC-3 compression with MPEG-2 Transport Stream/UDP transmission), realized in Texas Instruments Da Vinci TMS320DM8169 multimedia DSP device. Programming utilized the OpenMax IL multimedia component framework integrated with embedded Linux running on the ARM Cortex-A8 core of the device.
Developed Linux kernel driver to generate pulse-width-modulated signal for infra-red communication on ARM core of Da Vinci TMS320DM365 device.

7. January 2013 – February 2013
Consultant with PCTEL RF Solutions, Germantown, Maryland, U.S.A.
Ported physical layer DSP code written in C to new platform featuring object-oriented C++ design and new processing architecture, for application in wireless communication network test equipment (RF signal analysers). Target device was Texas Instruments TMS320C6416 running DSP/BIOS with development/debugging using Code Composer Studio v5 and v3.

8. July 2011-August 2012
Consultant with Texas Instruments, Dallas, Texas, U.S.A.
Developed new software component/module to suppress noise in wideband speech at 48 kHz for TI’s PurePath Studio DSP design tool. Target device was AIC3262 32-bit mini-DSP. Programming was in Assembler with simulation in Matlab.
Troubleshoot and resolve critical customer issues involving two-microphone noise cancellation system utilizing spectral processing, voice activity detection and filtering techniques.
Investigated efficient architectures for filterbanks (PR and near PR) including QMF, polyphase FIR, DFT, modified DCT and non-uniform IIR filterbanks.

9. July 2010 – April 2011
Consultant with IPC Systems, Fairfield, Connecticut, U.S.A.
Troubleshoot and resolve DSP-related problems on VOIP and TDM custom telephony systems. Add new features in embedded system to customer requirements. Integrate, test and evaluate audio DSP algorithms on multiple DSPs in line and station cards. Investigated algorithms included acoustic echo cancellation, G.168 line echo cancellation, G.729 and G.711 voice compression and IIR/FIR highpass filtering. Code development using C language and real-time debugging were performed on TI Code Composer Studio IDE for TMS320C6412 and C5509 devices, with MontaVista Linux and VxWorks embedded operating systems running on PowerPC control processors.

10. March 2009 – February 2010
Software Engineer with Blonder Tongue Laboratories Inc., Old Bridge, New Jersey, U.S.A.
Develop embedded software for digital video/IPTV distribution products. Developed embedded C code on NIOS-2 soft processor running embedded Linux (uCLinux) for web-browser based control and command of IP-based TV systems (Thomson HDTV satellite receivers) using SOAP and MDNS communication
protocols, TCP-UDP networking, CGI scripts and HTML web page design. Host system for development was Linux (Fedora 10 and CentOS 5).
Developed embedded C code for real-time synthesis of digital signal waveforms for data transmission in the vertical blanking interval of NTSC television signal.
Decoded/extracted data in real-time from MPEG-2 Transport Stream. The code was developed for ST20 core in MPEG-2 HDTV Decoder SoC (STi7707/STi7710) device. Development host was Cygwin on PC.

11. July 2008 – December 2008
Consultant with Intrasonics Ltd., Cambridge, U.K.
Development and integration of DSP audio algorithm in C software for real-time digital satellite TV set top box (STB) receiver.
Converted from floating point C/C++ and Matlab reference codes to fixed point C/C++ code for realtime implementation of above algorithm on 32-bit ARM 11 processor in mobile handset running Symbian OS. Processes implemented included cross-correlation, FEC channel decoding, bit sync and frame sync detection.

12. January 2008 – April 2008
Consultant with D&M Premium Sound Solutions, Leuven, Belgium (formerly Philips Sound Solutions)
Development of DSP stereo audio processing algorithms and modules for use in consumer portable wireless audio products. The work involved real-time implementation on CSR’s Bluecore multimedia chip which contains a 24-bit fixed-point DSP (Kalimba), 16-bit ARM and Bluetooth wireless interface. The development was performed using Assembler and C with validation using Matlab scripts and Simulink models.
Converted from floating-point models to fixed-point systems.
Implemented optimized FIR filters and IIR cascaded biquad structures on DSP. Simulated and analysed finite-word effects and scaling of the filters using Matlab/Simulink.

13. July 2007 – December 2007
Consultant wth GN Resound, Copenhagen, Denmark
Investigated DSP algorithm for fast system identification and initialisation of adaptive FIR acoustic echo cancelling filter in Hearing Aid. The objective was to implement this in a custom low-power 16-bit DSP. Investigation was done using Matlab/Simulink software and D-Space Matlab hardware.
Converted code from DSP Assembler to C for real-time execution on a custom DSP in Hearing Aid audio application.

14. October 1998-March 2007
Senior Engineer at Corporate Computer Systems Inc. dba Musicam USA, Holmdel, New Jersey.
Lead development of Musicam USA broadcast-quality audio codec products. This includes architectural design, schematic design, prototyping and debugging.
Develop DSP software (Assembler and C languages), associated FPGA firmware and hardware circuitry for real-time implementation of audio compression algorithms, multiplexing and transportation over various networks (E1, T1, ISDN, X.21, V.35, IP, Ethernet, RS-232).
Integrate third-party DSP algorithm software into Musicam platforms. Audio coding algorithms implemented included MPEG-1 Layers 2 and 3, G.722, J.41, J.57.
Develop embedded C software in VxWorks environment for command and control of audio codec systems, using RS-232, Ethernet links and add features to enhance system performance. .

15. 1996-1998
Consultant based in Melbourne, Australia.
Consultant to Corporate Computer Systems (6 months).
Consultant to Southern Group Ltd., in Perth, Western Australia.
Developed prototype of multi-channel ADPCM audio coding system using Analog Devices DSP processor with AT bus interface to PC Investigated/designed multi-rate filters for sampling rate conversion.

16. 1989-1996
Principal Engineer at Telstra Research Laboratories, Melbourne, Australia
Led research team in video compression and communication over ISDN, packet- based Metropolitan Area Network (MAN).
Led Telstra team in collaborative project with Texas Instruments Australia to develop H.261 video compression codec using array of TI DSPs (TMS320C30)Led the development of packetiser for video-audio communication over Ethernet/MAN.
Develop demonstration systems to show feasibility and applications for new multimedia services.
Represent Telstra in meetings and conferences locally and overseas. Chairman of Australian workshop on multimedia services and applications development.

17. 1986-1989
Senior Engineer at Thorn-EMI Central Research Laboratories, Hayes, Middlesex, England
Performed detailed research and investigation of video coding algorithms for High Definition Television (HDTV) systems. Techniques investigated included DCT, motion estimation/compensation, prediction, entropy coding, vector quantisation. Compared performances of various coding systems including scalable systems e.g. pyramid coding, sub-band coding. Investigated techniques for reduction of block effects. Simulated pre and post processing methods e.g. anti-alias filtering, temporal filtering, noise filtering
Simulated image processing methods which include edge detection/enhancement, sub-band decomposition/synthesis and median filtering.
Represent company at meetings of international HDTV alliances

PLATFORMS/CHIPSETS AND OPERATING SYSTEMS EXPERIENCE
1. DSPs – Texas Instruments TMS320DM81xx, TMS320DM365, TMS320C64xx ,TMS320C55xx, AIC3262, Freescale DSP560xx, DSP563xx, Analog Devices ADSP21xx, CSR’s Kalimba DSP in Bluecore BC-5MM chip
2. ARM Cortex A-9 dual-core, ARM Cortex-A8, ARM11, ARM920T, ARM 926EJ, ST 32-bit embedded processor cores
3. Microprocessors/Microcontrollers – Altera Nios II, PowerPC 860, Atmel, Infineon, Z-80
4. Programming/Simulation Languages – C, C++, Assembler, Matlab, Simulink, Modelsim
5. RTOS – DSP/BIOS, uClinux, Linux 3.9 SMP, MontaVista Linux, ST Microelectronics, Symbian OS, VxWorks
6. IDEs – ARM DS-5, TI Code Composer Studio, TI Purepath Studio, Eclipse CDT, Nios 2 SBT, Carbide C/C++ , S60 3rd Edition SDK, Wind River Tornado, CSR Bluelab, Microsoft Visual Studio 2013, Intel IPP functions/primitives
7. D-Space Matlab real-time simulation hardware
8. Target Compiler Technologies C and Assembler development tools
9. PC OS – Linux (Ubuntu 12.04 LTS, Fedora 10, CentOS 5), Cygwin, Windows 7, XP, Vista
10. FPGAs/PLDs – Altera Cyclone 5, Cyclone 3 FPGAs and EPLDs, Xilinx CPLDs, Lattice EPLDs
11. FPGA Development – Altera Quartus II 14.0,Qsys,VHDL, AHDL, Schematic Design, Xilinx ISE
12. SoCs /ASICs- ST Microelectronics STi 7707/7710 HDTV Decoder, Conexant CX2415X MPEG TV Decoder chip, Wiznet TCP-IP Chip
13. Cadence OrCAD Capture circuit design software
14. Source Control – Clearcase, SVN, Perforce, SourceSafe, Bitbucket